Last-level cache (LLC)
Beginner
The biggest memory on the chip, shared by all the cores. It is the last stop before the slow trip to main memory.
Novice
The final, largest level of on-chip cache, shared by all the cores (often called L3). It is usually split into slices spread across the chip, with each memory address assigned to one slice.
Expert
A banked, shared cache sliced across the interconnect, with an address hash choosing the slice; it often hosts the coherence directory or snoop filter. Inclusive or non-inclusive of the private caches; its slice distance is part of the NUMA picture on big dies.
Explained in Multicore and vector units (Architectures).
See also: Cache, Cache coherence, NUMA (non-uniform memory access).