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Beginner
A tiny insulating plug between the gate and the source and drain, tucked between the stacked ribbons.
Novice
Small pieces of insulator placed at the ends of the silicon-germanium layers, between neighboring nanosheets. They keep the gate metal that later fills those gaps away from the source and drain.
Expert
Formed by a lateral cavity etch of the SiGe ends, dielectric deposition and etch-back. It cuts gate-to-S/D capacitance and shields the S/D epitaxy during channel release. Too shallow leaves capacitance; too deep adds extension resistance; published work puts the optimum depth under about 5 nm.
Explained in Fins and nanosheets (Transistors).
See also: Channel release, Si/SiGe superlattice.