Inferred latch
Beginner
An accidental memory the tool builds when the design forgets to say what a signal should be in some situation.
Novice
A storage element a tool adds by accident. If code meant to have no memory leaves a signal unassigned in some case, the signal must keep its old value, and keeping a value needs memory: a latch, which passes its input through while enabled and freezes when not.
Expert
Usually a bug: unintended state that complicates timing analysis and test. Default assignments at the top of always_comb, a default branch in every case, and lint (Verilator’s LATCH warning) catch it. A latch you do want goes in always_latch.