IJTAG (IEEE 1687)
Beginner
A standard way to reach the many small test circuits hidden inside a chip through its test plug.
Novice
IEEE 1687 (internal JTAG) defines a network of internal test chains behind the JTAG port that can be reconfigured to reach the chip’s built-in test and monitoring circuits, such as memory testers and temperature sensors.
Expert
Segment insertion bits (SIBs) open or close network segments so only the instruments in use sit in the scan path. ICL describes the network; PDL describes instrument operations, which tools retarget to chip-level patterns.
Explained in Design for test (Design Flow).
See also: Boundary scan (IEEE 1149.1, JTAG), Memory BIST (MBIST).