Ideal clock
Beginner
A pretend clock that reaches everything at once. Engineers use it before the real clock wiring exists.
Novice
A stand-in clock used before the clock network exists: the timing tool pretends it reaches every flip-flop instantly, or after a delay the engineer estimates. Synthesis and placement time the design against it.
Expert
In ideal mode, set_clock_latency, set_clock_transition and an enlarged set_clock_uncertainty describe the tree that doesn’t exist yet. Forgetting to remove them after CTS counts the tree twice.