Glossary

High-level synthesis (HLS)

Beginner

A tool that writes the detailed chip description for you from a program written in a language like C++.

Novice

A tool that writes RTL from an algorithm in C, C++ or SystemC. The input says nothing about clock ticks; the tool decides which operations happen in which tick and how much hardware to build for them.

Expert

Works in three steps: scheduling assigns operations to clock cycles, allocation chooses how many hardware units to build, and binding maps each operation onto a unit. Directives from the designer steer the trade between fewer cycles and less hardware.

Explained in RTL design (Design Flow).

See also: Register-transfer level (RTL).

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