FPGA–ASIC gap
Beginner
How much bigger, slower and more power-hungry an FPGA is than a custom chip doing the same job. It is the price of being able to rewire it.
Novice
The ratios of area, delay and power between a circuit built in an FPGA and the same circuit as a custom chip on the same process. A classic 90 nm study measured about 35× the area, 3–4× the delay and 14× the dynamic power for plain logic.
Expert
Measured by implementing identical RTL both ways on matched processes (Kuon & Rose: 35× area, 3.4–4.6× delay, 14× dynamic power, logic only). Hard blocks narrow area and power far more than delay; the gap for a whole product depends on how much of it maps to hard IP.