Fault simulation
Beginner
Running a computer model of the chip with each pretend flaw added, to see which tests would catch it.
Novice
Simulating the circuit once without faults and again with each modeled fault inserted, and comparing the outputs, to find out which patterns detect which faults and what the coverage is.
Expert
Serial, parallel (bit-parallel over faults or patterns), deductive and concurrent algorithms exist. PPSFP (parallel-pattern single-fault propagation) dominates for full-scan logic; concurrent simulation handles general timing and sequential models. Fault dropping speeds it up but is turned off for diagnosis.
Explained in Design for test (Design Flow).
See also: ATPG (automatic test pattern generation).