Refresh (DRAM)
Beginner
Reading and rewriting every bit of a DRAM chip many times a second, before its leaking charge fades away.
Novice
Because DRAM capacitors leak, every row must be read and written back periodically. Standard DRAM refreshes each row at least every 64 milliseconds.
Expert
The controller issues an auto-refresh command every tREFI (7.8 µs below 85 °C); each one blocks the rank for tRFC while a batch of rows is activated and restored. The interval is set by the leakiest cells, so refresh costs bandwidth and energy that grow with density.