Glossary

Die-to-die link

Beginner

The very short wires that let two chips in one package talk almost as if they were one chip.

Novice

An interface designed for the few millimeters between dies in one package: many parallel, simple lanes at moderate speed, instead of a few very fast lanes built to cross a circuit board.

Expert

Parallel single-ended lanes with a forwarded clock, little or no equalization and low latency. Judged by bandwidth per mm of edge or per mm², energy per bit, latency and reach. UCIe standardizes one; NVIDIA’s NV-HBI and AMD’s Infinity Fabric links are proprietary examples.

Explained in Packaging and chiplets (Systems).

See also: UCIe, SerDes.

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