Design for test (DFT)
Beginner
Extra parts built into a chip so a test machine can quickly check each copy for flaws.
Novice
Design techniques that make it cheap to create, run and judge manufacturing tests. The main ones link the chip’s internal memory cells into test chains, give memories their own built-in testers, and add a standard test port.
Expert
Test structures added mostly to the gate-level netlist after synthesis: scan chains and compression for logic, memory BIST, logic BIST where needed, and JTAG/IJTAG for access. Judged by fault coverage, pattern count, test time, and what the structures cost in area, timing and power.
Explained in Design for test (Design Flow).
See also: Scan chain, ATPG (automatic test pattern generation).