Contacted poly pitch (CPP, gate pitch)
Beginner
The spacing between neighboring transistor gates on a chip, from the middle of one to the middle of the next.
Novice
The center-to-center distance between neighboring gates, with room for a contact between them. Together with the metal pitch it sets how small a logic cell can be.
Expert
Gate length + 2 spacers + source/drain contact width. It scaled about 0.85–0.9× per node in the FinFET era (ASAP7 assumes 54 nm) and, with M1/M2 pitch and track count, sets cell area. The ‘G’ in IRDS’s G-M-T density notation.