Beginner

A steady tick signal that tells every memory cell on the chip when to update, like a metronome.

Novice

A signal that switches between 0 and 1 at a steady rate, for example a billion times a second (1 GHz). Each rise from 0 to 1 is a clock edge, the moment flip-flops take in new values. The time between edges is the clock period.

Expert

The time reference of a synchronous design. Every path between flip-flops must settle within one period, minus margins, so the slowest path sets the highest usable clock frequency. Chips usually have several clocks, which divides them into clock domains.

Explained in RTL design (Design Flow).

See also: Flip-flop (register), Clock domain.

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