Clock tree synthesis (CTS)
Beginner
The step that builds a branching network of wires and small amplifiers to carry the clock’s tick to every memory cell on the chip.
Novice
The layout step, run after the logic cells have been placed, that builds the network carrying the clock to every flip-flop. It inserts and places small amplifier cells (clock buffers) and connects them so the clock tick arrives everywhere at nearly the same moment, with a sharp edge.
Expert
Builds each clock network (cluster the endpoints, choose a branching structure, insert and size buffers, balance branch delays) against targets for skew, latency and edge rate, then re-times the design with the real clock delays and repairs setup and hold. Commercial tools: Cadence Innovus, Synopsys IC Compiler II and Fusion Compiler; open source: OpenROAD’s TritonCTS.
Explained in Clock tree synthesis (Design Flow).
See also: Clock skew, Insertion delay (clock latency).