Insertion delay (clock latency)
Beginner
How long the clock tick takes to travel from where it enters the chip to a memory cell.
Novice
How long the clock tick takes to travel from where it is defined (usually the chip’s clock pin) to a flip-flop. Delay before the chip pin is source latency; delay through the on-chip network is network latency.
Expert
Latency matters beyond skew. The part of two flip-flops’ clock paths that is not shared gets variation margins applied to it, so longer latency costs slack; it also collects more jitter and burns more power. Before CTS it is estimated with set_clock_latency; afterwards the timer computes it.
Explained in Clock tree synthesis (Design Flow).
See also: Propagated clock, On-chip variation (OCV).