Cell-aware test
Beginner
Testing for tiny flaws inside the chip’s smallest building blocks, not only on the wires between them.
Novice
A way of testing for defects inside the library’s building blocks (cells). Each cell’s internal layout is checked for likely shorts and breaks, each one is simulated in detail, and the result becomes a condition on the cell’s pins that test software can aim at.
Expert
Each likely defect in a cell layout is SPICE-simulated, and the input conditions that expose it become 1-time-frame (static) or 2-time-frame (delay) faults at the cell pins. It catches parts that pass stuck-at and transition tests.