Asynchronous FIFO
Beginner
A waiting line between two parts of the chip with different clocks: one side adds items, the other removes them at its own pace.
Novice
A small first-in, first-out queue between two clock domains. One side writes items in at its pace and the other reads them out at its own. Only the two position counters (where to write next, where to read next) cross between the clocks, through synchronizers.
Expert
The standard way to move a stream of multi-bit data between clocks. The pointers cross in Gray code, so a pointer caught mid-change reads as either its old or its new value. The full and empty flags are therefore a cycle or two late, but never wrong.
Explained in RTL design (Design Flow).
See also: Gray code, Clock domain crossing (CDC).