Assertion (SVA)
Beginner
A rule written into a design or a test. It sounds an alarm the moment the rule is broken.
Novice
A rule written into the design or testbench and checked continuously while the design runs, such as “a reply always comes within four clock cycles.” If it is ever broken, the simulator reports where and when. SystemVerilog Assertions (SVA) is the standard notation.
Expert
Immediate assertions check a condition at one moment; concurrent ones describe sequences over clock cycles and are understood by both simulators and formal tools. Engineers write assume for rules about inputs, assert for what must hold, and cover to show that a scenario can happen at all.
Explained in Verification (Design Flow).
See also: Formal verification, Functional coverage.