At a glance
Where the flow bends
- 01Specification
Before anyone draws a circuit, the team decides who is allowed to see the design and which factories may build it.
Before design starts, the team settles three things: which U.S. export law covers the design (the State Department’s ITAR rules for weapons technology, or the Commerce Department’s EAR rules for items with civilian and military uses); whether the chip must be built only by government-approved “trusted” suppliers; and how it will be supported for decades, including what happens when its parts go out of production.
Classify early. A custom chip (ASIC) programmed for an item on the U.S. Munitions List is itself listed, in Category XI(c)(1), so its design files (the RTL code, the gate-level netlist and the GDS layout) are controlled technical data from day one. Write into the spec the trusted-supplier path required by DoD Instruction 5200.44, the plan for parts going out of production (DMSMS), and a threat model listing where an attacker could interfere: third-party IP, design tools, the factory, assembly and distribution.
- 02Architecture
Teams choose between a store-bought chip that can be rewired and a chip made just for this job. The parts that hold secrets get walled off.
A central choice is between a reprogrammable chip bought off the shelf (an FPGA) and a custom chip (an ASIC). An FPGA avoids the large up-front cost of a custom chip and can be updated in the field; a custom chip is smaller and uses less power. Security functions often get their own walled-off section of the chip.
Trade one-time engineering cost (NRE: design effort and the photomasks a custom chip needs), volume, size, weight and power, and supply-chain exposure. DARPA’s AISS program formalized a split into an application partition and a security partition, sized against four attack surfaces: side channels, reverse engineering, supply-chain attacks and malicious hardware.
- 03RTL design
Engineers check where every borrowed building block came from. Someone could have hidden an extra circuit inside one.
Chips reuse ready-made circuit blocks bought from other companies, called third-party IP (intellectual property). Each block’s origin is reviewed. Blocks delivered encrypted are a concern, because you must trust a supplier whose design you can’t inspect.
Prefer IP whose source you can read, record every block’s origin, and treat encrypted (“locked”) IP as an unverified dependency in the threat model: a circuit that does nothing until triggered could sit inside it unseen.
- 04Verification
Testers hunt for circuits that do nothing in normal use but could wake up on a secret signal.
As well as checking that the design works, testers hunt for hardware Trojans: hidden extra circuits that do nothing in normal use but switch on under a rare, secret condition. They look for logic that is rarely or never exercised, and for paths to the chip’s outputs that the specification doesn’t call for.
Add Trojan-focused checks to coverage closure: find signals that tests almost never activate, review logic that never changes value across the regression suite, use formal tools to prove no unexpected path reaches a sensitive output, and compare against a trusted reference model. After manufacture, compare power and timing measurements (side channels) against known-good chips, and take sample chips apart (reverse engineering) to compare them against the design.
- 05Logic synthesis
Some designs add a secret key to the circuit, like a password. A stolen copy gives wrong answers without it.
Some designs add a secret key to the circuit, a technique called logic locking. Extra gates are inserted so the chip computes correctly only once the right key is loaded after manufacture. A stolen or overproduced copy without the key gives wrong answers.
Locking costs area and timing, and its security record is poor: the SAT attack, which pairs a working chip with a logic solver, recovers the keys of the early XOR/XNOR schemes, and later schemes remain in an attack-and-defense cycle. Treat it as one layer among several.
- 11Routing
A design can be split between two factories. One builds the bottom layers, and a trusted one adds the top wiring.
A chip is built in layers: transistors at the bottom, with a stack of metal wiring layers above them. In split manufacturing, one factory builds the transistors and lower wiring, and a trusted factory adds the upper wiring, so the first factory never sees all the connections.
Ordinary placement and routing put connected cells close together, so an attacker holding the lower layers can guess many missing connections by proximity. Defenses move cells or pins (proximity perturbation), push wires up into the hidden layers (wire lifting) or disguise the layout (obfuscation), each at a cost in power, performance and area. Splitting at a lower metal layer hides more connections but costs more.
- 13GDS & tapeout
The finished design goes only to an approved factory. Every handoff is tracked, like evidence in a court case.
The finished layout file (GDS) goes only to a factory accredited by the Defense Microelectronics Activity (DMEA), with every handoff recorded. Mask making, fabrication, packaging and testing may each need their own accreditation.
Plan the tapeout around accredited sources for masks, fabrication, post-processing, packaging and test; controlled transfer of the ITAR technical data; and lifetime buys or re-fabrication options for when the process or package goes away.
A chip in a radar or a missile has to do its job and nothing else, often for 20 or 30 years. The military also has to be sure of three things. Nobody added a hidden circuit. The design didn’t leak to the wrong country. And the parts on the shelf are real.
So every step of building a defense chip comes with one extra question: who touched this, and can we prove it? A program called makes sure secret chips are made only by approved companies.1 Export laws such as decide who may even look at the design files.2
Making a chip is a long chain of steps. Engineers write a specification, describe the circuit in code, turn that code into a list of logic gates, arrange the gates on the silicon, and send the final layout file (called GDS) to a factory. Many companies may be involved: suppliers of ready-made circuit blocks, makers of design software, the factory, packaging and test houses. For a military chip, every link in that chain is a place where someone could steal the design or tamper with it.
The U.S. responds with rules about who may handle the chip. A Defense Department instruction, 5200.44, requires that chips custom-designed or tailored for a military use be bought from a accredited by the Defense Microelectronics Activity (DMEA). DMEA accredits suppliers of chip design, brokering, mask making (the stencils used to print the chip), fabrication, packaging and test.1
Export law reaches the design files too. The U.S. Munitions List covers “Application Specific Integrated Circuits (ASICs) and Programmable Logic Devices (PLD) programmed for defense articles.” An ASIC is a custom chip, “developed and produced for a specific application or function regardless of number of customers.” Custom chips for less sensitive military items fall under the Commerce Department’s rules instead.2 Showing the controlled design files to a foreign national, even inside the U.S., counts as an export, called a .3
DMEA defines trust as confidence gained by “assessing the integrity of the people and processes used to design, generate, manufacture and distribute” critical components. A trusted source must provide a chain of custody, avoid supply disruption, prevent tampering, and protect parts from reverse engineering.1
The National Academies list three design-phase exposures:5
- Third-party IP. Chips reuse ready-made blocks (interfaces, microcontrollers, memories), often delivered encrypted, which means “the user must trust the provider.” An adversary could plant circuit elements that change nothing until an external command triggers them.
- Protection of critical design information.
- Dependence on design software, the tools that turn code into layout.
The accredited path doesn’t cover every process or package a program wants, so design-side techniques fill gaps: , , Trojan-focused verification and separate security sections of the chip. None of them replaces a trusted flow; each narrows what an untrusted party can learn or change.
Export control shapes the engineering environment. Category XI(d) of the Munitions List covers the technical data directly related to the controlled chips, so the RTL, netlists and layout of an ITAR chip are controlled data.2 Because any release to a foreign person in the U.S. is an export to every country where that person holds citizenship or permanent residency, accounts, servers and design reviews all fall inside the control.3
An ordinary flow: every handoff is a place to steal or tamper. Tap a step.
Four worries shape a defense chip:
- Secrets. The design is secret, so only approved people may see it.
- Sabotage. Someone could slip a , a hidden harmful circuit, into the design.
- Fakes. In 2012, the U.S. Senate found over a million suspect fake parts headed for the military.4
- Time. Weapons stay in use so long that the chips inside stop being made first.
Hidden circuits. A is a deliberately hidden change to a chip. The simplest has two parts: a trigger that waits for a rare condition, and a payload that then changes what the chip does, leaks information or shuts it down. It can be added during design, during manufacturing, or inside a ready-made block bought from another company. Ways to find one include tests aimed at rarely reached conditions, measuring tiny differences in power or timing, and taking chips apart to compare them with a trusted reference.12
Fakes. Counterfeiters recycle discarded chips, alter them and sell them back into the supply chain; the parts may not work as specified. DARPA’s SHIELD program aimed to make this unprofitable with a 100 µm × 100 µm encrypted “dielet,” a tiny chip placed inside the package of the real one to prove it is genuine.8
Going out of production. A 2017 Defense Science Board report, quoted by the National Academies, found that about 70 percent of the electronics in a weapons system are obsolete or out of production before the system is fielded.5 Managing this is called .
Low volume, high cost. DARPA notes that a custom chip can cost up to $100 million and take more than two years to design. So defense engineers often use general-purpose chips plus software instead, which uses more power than a small drone or a soldier’s batteries can easily supply.6
FPGA or ASIC. The choice sits where these pressures meet. An avoids the cost of custom masks and can be updated in the field, and the National Academies report FPGAs in the F-35’s radar, communication and navigation systems.5 But an FPGA is a commercial part from a global supply chain, and the same report calls public contract announcements that name specific FPGA purchases for the F-35 a poor practice, because they give an adversary insight into what is inside U.S. systems.5 A custom ASIC wins when power and size matter on small platforms, the case DARPA’s CRAFT program set out to make affordable by shortening custom-chip design from years to months.6
Design speed. Large commercial chip companies split the work among big teams of specialists; defense teams lack those resources, and DARPA’s IDEA program cites defense hardware design cycles two to three times longer than commercial ones. IDEA aimed at a compiler that goes from source code to GDSII layout with no human in the loop in under 24 hours.7 Fast, automated flows help with obsolescence too: a design that can be re-run on a new process is easier to sustain than one tied to a process that has closed.
Radiation. Systems that fly high or must survive nuclear environments add radiation-hardening targets to the spec. Those methods are covered on the Space page.
With a 16-bit trigger, 10,000 random tests hit it with probability 14.2%. That is why Trojan hunts aim tests at rare conditions.
Most steps look the same as for any other chip. What changes is who may work on it, what extra checks happen, and where it is built.
During design, engineers check every borrowed building block. They also hunt for circuits that don’t belong. Some designs get a secret key, so a stolen copy won’t work.
At the end, the files go only to an approved factory, and every handoff is logged.
| Stage | What defense adds |
|---|---|
| Specification | Which export law applies, whether trusted suppliers are required, a plan for decades of support |
| Architecture | Off-the-shelf FPGA or custom ASIC; a separate security section |
| Writing the circuit code | Checking where every bought-in block came from |
| Verification | Hunting for hidden circuits: rare triggers, unexplained logic |
| Turning code into gates | Optional logic locking with a secret key |
| Placement and wiring | Optional split manufacturing across two factories |
| Sending to the factory | Layout goes only to an accredited trusted supplier, with a record of every handoff |
DARPA’s AISS program divided the chip into two sections, an application processor and a security section, built to resist four kinds of attack: side channels (learning secrets from power use or timing), reverse engineering, supply-chain attacks and malicious hardware.9
Logic locking, in its simplest form, puts an XOR gate on an internal wire, with one input fed by a secret key bit. With the right key bit the wire carries its normal value; with the wrong one, it is flipped and some outputs come out wrong.11 Split manufacturing sends the transistors and lower wiring layers to an advanced but untrusted factory and the upper wiring layers to a trusted one, so the first never sees the full wiring.10
Logic locking and the SAT attack. The first scheme, by Roy et al. in 2008, randomly added XOR and XNOR gates fed by new key inputs. The attack by Subramanyan et al. assumes the attacker has the locked netlist and a working, unlocked chip to query (the “oracle”). It runs in a loop:11
- Build two copies of the locked circuit with separate keys and the same inputs, and ask a SAT solver (a program that finds values making a logic formula true) for an input where the two copies disagree. That input is a distinguishing input pattern.
- Apply that input to the working chip and record the correct output.
- Add the constraint “with this input, the output must be this” for both keys. Every key that gives a wrong answer is now ruled out.
- Repeat until the solver finds no input on which the remaining keys disagree. Any key left behaves like the correct one.
Its arrival “marked a turning point.” Later schemes try to rule out fewer keys per loop or build circuits that are hard for SAT solvers, and new defenses keep being proposed and countered.11 Key gates also sit on timing paths, so locking has to be inserted before final timing closure and checked for equivalence with the key applied.
Split manufacturing and proximity. Placement tools tend to put connected cells close together, because that saves area, wire length and delay. An attacker holding the lower layers can therefore guess a missing connection by pairing nearby input and output pins; this is the proximity attack. The more pins left to connect, the more likely a guess is wrong, so splitting at the lowest metal layer possible gives the most security, at more overhead.10 Defenses fall into three groups: proximity perturbation (moving cells or pins), wire lifting (forcing wires up into the hidden layers) and layout obfuscation. Published results disagree sharply: some studies claim near-perfect reconstruction of the netlist, others only marginal success.10 In practice the split layer becomes a routing constraint, because sensitive nets must be lifted above it, which costs vias, congestion and timing.
Trojan-aware verification. A Trojan trigger is built to be a rare event, which is why normal testing misses it.12 Coverage closure therefore adds rare-condition analysis, a review of logic that never toggles in regression, and formal checks that no unintended path reaches keys or outputs. After manufacture, side-channel comparison against known-good parts and reverse engineering of samples close the loop.12
Data handling. Because the design database is ITAR technical data, the design environment itself is in scope: who has accounts, where licenses and compute run, and how the GDS travels to the mask shop.3
Wrong key bit: the key gate flips its wire, and 4 of 8 input rows give a wrong output.
In 2012, the U.S. Senate spent a year looking into fake parts. It found fakes in the Air Force’s biggest cargo plane, in parts meant for special forces helicopters, and in a Navy patrol plane.4 One supplier alone sent about 84,000 suspect parts toward the military.4
The lesson: a perfect design is useless if a fake chip ends up in its place. That’s why defense teams care so much about where every part comes from.
The committee identified about 1,800 cases involving more than a million suspect parts. It traced well over 100 of those cases back through the supply chain and found more than 70 percent of the suspect parts came from China.4 Parts from one supplier in Shenzhen reached collision-avoidance systems intended for the C-5AMP and C-12 transport planes and the Global Hawk drone, and assemblies for the P-3 patrol plane and the Special Operations A/MH-6M helicopter.4
Counterfeits gather where military and commercial timescales differ. Commercial chips are replaced by newer models every few years, and the National Academies describe a commercial supplier that assumes counterfeits only appear once its parts are already outdated. That assumption fails for military systems kept in service for decades.5 A defense program buying an old part from a broker is exactly that case.
The report also shows how fakes get through. The roughly 1,800 suspect cases involved more than 650 supplying companies, each with its own network of suppliers. Parts bound for one Navy helicopter changed hands five times before a subcontractor bought them. Testing varied widely: in one case a China-based supplier chose a sample of 18 chips for testing, and once those passed, sold the buyer more than ten thousand without further independent testing.4
Design responses work at three levels:
- Depend less on parts that will disappear. Once a part is out of production, the National Academies note, supply depends on lifetime buys or vetted brokers.5 Keeping RTL portable and documented, so the function can be rebuilt on a new process, is a DMSMS strategy as much as a design one.
- Make authenticity checkable in the field. SHIELD’s dielet combined passive sensors that record attempts to de-solder or open the package, an encryption engine, and near-field power and communication, so a probe could check a part’s origin against a server.8
- Keep custom parts inside the accredited flow, where chain of custody is the control.1
The case also shows why “trusted” is a property of the whole lifecycle. A design that passes every Trojan check, built in an accredited fab, can still be defeated twenty years later by a re-marked part from the gray market.
The parts enter the supply chain. Their origin isn’t visible to later buyers.
Sources
Show Hide 12 sources
- Trusted Supplier ProgramDefinition of trust, the Instruction 5200.44 requirement, accreditation categories, Trusted Foundry services.
- 22 CFR § 121.1 The United States Munitions List (Category XI, Military Electronics)USML XI(c)(1): ASICs and PLDs programmed for defense articles; ASIC definition; 600-series ASICs under ECCN 3A611.f; XI(d) technical data.
- 22 CFR § 120.50 ExportReleasing technical data to a foreign person in the U.S. is a deemed export, to every country of citizenship or permanent residency.
- Senate Armed Services Committee Releases Report on Counterfeit Electronic Parts1,800 cases, over 1 million suspect parts, affected platforms, sourcing and testing weaknesses.
- The Growing Threat to Air Force Mission-Critical Electronics: Lethality at Risk: Unclassified Summary (Discussion of Selected Topics)Design-phase threats (third-party IP, CAD tools), FPGA use in the F-35, contract-announcement OPSEC, obsolescence, counterfeits and lifetime buys.
- Circuit Realization at Faster Timescales (CRAFT)Custom IC cost and schedule; DoD reliance on general-purpose circuits.
- Intelligent Design of Electronic Assets (IDEA)DoD design cycles 2–3× longer than commercial; 24-hour no-human-in-the-loop layout goal.
- Supply Chain Hardware Integrity for Electronics Defense (SHIELD)Counterfeit ICs; 100 µm × 100 µm authentication dielet.
- Automatic Implementation of Secure Silicon (AISS)Security partition, four attack surfaces, automated secure design flow.
- A Survey on Split Manufacturing: Attacks, Defenses, and ChallengesFEOL/BEOL split, proximity attacks, split-layer trade-off, defense categories, disagreement between studies.
- High-Level Approaches to Hardware Security: A TutorialLogic locking with key gates; step-by-step walk-through of the SAT attack.
- Hardware Trojans in Chips: A Survey for Detection and PreventionTrojan structure (trigger, payload), insertion points, detection methods.