UVM (Universal Verification Methodology)
Beginner
A popular set of rules and building blocks for chip tests, so parts can be reused from one chip to the next.
Novice
A standard library and set of conventions for building testbenches out of reusable parts, written in the SystemVerilog language and standardized as IEEE 1800.2.
Expert
Supplies standard component types (agents containing drivers, sequencers and monitors), fixed run phases, a factory that lets a test swap a component for a variant without editing the rest, a configuration database and a register model. Reuse is the payoff; boilerplate and a steep learning curve are the cost.