Utilization (placement density)
Beginner
How full the chip’s floor is. 70% means parts cover 70% of the space and 30% is left open.
Novice
The share of the space for logic cells that the cells actually cover. Overall (core) utilization is an average; target density is the most any small area may be filled. Leaving a good part free gives room for wires and for the cells that timing repair adds later.
Expert
Global utilization is an average; local bin density and pin density are what cause trouble. A block can be 60% utilized overall and still have bins at the cap next to macros. Placers enforce a per-bin target density (OpenROAD gpl defaults to 0.7), and routability modes inflate cells where congestion is predicted.