TLB (translation lookaside buffer)
Beginner
A tiny, fast list of recent address translations, so the chip doesn’t have to look them up in memory every time.
Novice
A small cache of recent virtual-to-physical page translations. A hit translates in about a cycle; a miss triggers a page-table walk, one memory access per level.
Expert
Typically 32–128 highly associative entries at L1 plus a larger shared L2 TLB (Skylake: 64 and 1,536 for 4 KB pages). Reach = entries × page size; huge pages extend it. On x86 a hardware walker refills it; MIPS and Alpha used software.