Synthesizable subset
Beginner
The part of a chip-design language that a tool can turn into real circuits.
Novice
The parts of a hardware language that a tool can turn into real circuits. Time delays, printed messages and file reading are left out: they are useful when testing a design but mean nothing in hardware.
Expert
Codified for Verilog in IEEE 1364.1 and assumed by tools such as Yosys. Code outside it can simulate correctly and then be ignored or rejected by synthesis, so the gates behave differently from the simulation: a simulation/synthesis mismatch.