RTL-to-GDS flow
Beginner
The full chain of programs that turns a chip’s written plan into the final drawing sent to the factory.
Novice
The sequence of software steps from the design’s code (RTL) to the final layout file (GDSII): turn the code into logic gates, plan the chip’s area, lay out the power wiring, place the gates, build the clock wiring, route the remaining wires, and run the final checks.
Expert
In practice a set of scripts (Makefiles, Tcl, Python) that runs the tools in order, passes the design between them in a database or in files, and checks quality numbers such as timing, area and wiring congestion between steps before letting the run continue. OpenROAD-flow-scripts and LibreLane are open examples; companies build theirs starting from vendor and foundry reference flows.