RISC-V
Beginner
A free, open list of commands for chips. Anyone can build a chip that follows it, without paying for the right.
Novice
An open, royalty-free RISC instruction set begun at UC Berkeley in 2010 and now managed by the non-profit RISC-V International. A small base set of integer instructions plus optional standard extensions.
Expert
A modular load-store ISA: RV32I/RV64I base (32 integer registers, x0 hardwired to zero, fixed 32-bit encodings in six formats) plus extensions such as M, A, F, D, C and V, with no exposed delay slots.
Explained in Instructions and pipelines (Architectures).
See also: Instruction set architecture (ISA), RISC and CISC.