Power-aware simulation
Beginner
Testing what happens when parts of the chip switch off and back on to save battery.
Novice
Simulation that also models parts of the chip being switched off and back on to save power, following the chip’s power plan, so tests can check that sleeping parts don’t disturb the rest and wake up correctly.
Expert
Reads the UPF power intent, scrambles the state of powered-down regions, and models isolation, retention and level-shifter cells. It has to exercise the whole power sequence and the control logic around it. Slower than plain RTL simulation, and the unknown values it spreads make failures slow to trace.
Explained in Verification (Design Flow).
See also: UPF, isolation cell, retention flip-flop.