PLL (phase-locked loop)
Beginner
The part that makes the chip’s clock, the steady beat that keeps all the other parts in step.
Novice
A phase-locked loop: a circuit that takes a slower reference clock from outside the chip and generates the faster clock the logic runs on, locked in step with the reference.
Expert
A mixed analog and digital macro, usually bought or reused as IP. Its jitter is sensitive to supply and substrate noise, so floorplans keep it away from busy logic and give it a short, clean path to its reference-clock pin.