Metal stack
Beginner
The layers of copper wiring stacked above the chip’s tiny switches, like floors in a parking garage. Low floors have thin, tightly packed wires; high floors have thick, roomy ones.
Novice
The layers of metal wiring built on top of the transistors, numbered from M1 at the bottom to M10 or more at the top, separated by insulating glass and joined by vias. Lower layers are thin and tightly packed for short local connections; upper layers are thicker and wider, so they resist current less and suit long routes, clocks and power.
Expert
Pitch (the center-to-center spacing of wires) and thickness grow up the stack, so resistance per µm falls steeply from the lower layers to the upper ones. Promoting critical nets to upper layers, giving them wider wires and resistance-aware layer assignment all exploit that. At advanced nodes the lowest layers are printed with several masks and must run strictly in one direction, and power may move below the transistors or to the back of the wafer.