Load-use hazard
Beginner
When a step needs a number that is still on its way from memory. Even with the shortcut, it has to wait a moment.
Novice
A load followed directly by an instruction that uses the loaded value. The data only arrive at the end of the memory stage, one cycle too late for the next instruction’s execute stage, so the pipeline stalls for one cycle even with forwarding.
Expert
Load-to-use latency is two cycles in the five-stage pipeline (one for ALU-to-use), so the hazard unit inserts one bubble at distance 1. Compilers schedule an independent instruction into the slot; deeper pipelines and caches lengthen the distance.
Explained in Instructions and pipelines (Architectures).
See also: Forwarding (bypassing), Pipeline hazard.