Integrated logic analyzer
Beginner
A tiny recorder built into an FPGA design. It watches chosen signals and saves what happens around an event.
Novice
Debug logic added to an FPGA design. It samples chosen internal signals every clock into on-chip memory, stops after a trigger condition, and sends the samples to a computer to be viewed as waveforms. FPGA vendors ship their own versions.
Expert
An embedded capture core: probe ports, trigger comparators, a circular buffer in block RAM and readout over JTAG. It costs RAM, logic and a recompile, and depth × width limits what it sees. The custom-chip equivalent is a trace buffer.
Explained in From hardware code to bitstream (Architectures).
See also: Trace buffer, FPGA prototyping.