Gate-level simulation (GLS)
Beginner
Rerunning some tests on a later, more detailed version of the design, to catch problems the earlier version hid.
Novice
Rerunning some tests on the netlist, the version of the design after it has been turned into actual logic gates, sometimes with each gate’s real delay included. It catches problems that the higher-level description hid.
Expert
Runs either with zero delay or with delays from an SDF file (Standard Delay Format, written by the timing tools). Catches unknown-value bugs masked in RTL simulation, mismatches between how synthesis and simulation read the code, reset problems and test-mode issues. Slow, so teams run a short, targeted list.