Glossary

Full mesh

Beginner

Every chip has its own direct wire to every other chip.

Novice

A topology where each of pp chips has a direct link to each of the other p−1p - 1. No switch is needed, and any two chips are one hop apart.

Expert

Degree p−1p - 1, so the chip’s fixed lane budget is split p−1p - 1 ways: per-pair bandwidth falls as 1/(p−1)1/(p-1) and the domain size is capped by the port count (8 chips with seven links is typical).

Explained in Scale-up fabrics (Systems).

See also: Topology.

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