Floorplan
Beginner
The plan for a chip’s space: how big it is and where the big blocks go, made before the small parts are placed.
Novice
The plan of a chip’s physical layout, made before any of its millions of small parts are placed: how big the chip is, where its connections to the outside world sit, where the large ready-made blocks go, and which areas are reserved or kept clear. Tools save it as a file, usually DEF, that later steps start from.
Expert
The set of decisions every later layout step inherits: the outline, the rows that standard cells will sit in, I/O pin or bump positions, each macro’s location and orientation with a keep-out halo, blockages, power-domain regions and, when the chip is split into blocks, each block’s outline, pins and timing budget. Macro positions are rarely changed once fixed, so their quality limits timing, congestion and the power grid downstream.
Explained in Floorplanning (Design Flow).
See also: Die and core, Macro (hard macro), DEF.