False sharing
Beginner
When two cores use different numbers that happen to sit in the same block. The block bounces between them as if they were sharing.
Novice
Two threads write different variables that share a cache line. Coherence works per line, so each write invalidates the other core’s copy and the line ping-pongs, even though no data is actually shared.
Expert
A coherence-miss pathology: each write needs ownership of the whole line. Fixed by padding or aligning per-thread data to the line size (64 bytes, or more where lines or adjacent-line prefetch pair lines), or by per-thread copies merged later.
Explained in Caches and coherence (Architectures).
See also: Cache line (block), MESI protocol.