Deterministic execution
Beginner
A chip that does exactly the same steps, in exactly the same time, every time you run the same job.
Novice
Execution in which the timing of every operation is known in advance. The compiler, not the hardware, decides when each piece of data moves and each instruction runs, so there are no caches or traffic jams to make the timing vary.
Expert
Achieved by removing reactive hardware (caches, arbiters, dynamic routing, replay) and exposing fixed latencies to a compiler that schedules every cycle. Multi-chip versions need aligned clocks or counters and paced, error-corrected links.
Explained in Wafer-scale and SRAM-heavy designs (Architectures).
See also: deterministic latency, Bulk synchronous parallel (BSP).