CPLD (complex programmable logic device)
Beginner
An older kind of programmable chip: a few small blocks of AND and OR gates, joined by one big switch grid.
Novice
A programmable chip made of several PAL-like sum-of-products blocks joined by one programmable interconnect matrix. It keeps its setup when powered off and has short, predictable delay, but limited size.
Expert
Macrocell blocks with programmable AND arrays around a central switch matrix, usually EEPROM configured; one extra interconnect stage keeps timing near a PAL’s. Two-level logic grows costly for large multi-level circuits.