Clock transition (slew)
Beginner
How sharp the clock tick is: a crisp click or a slow fade.
Novice
How long the clock signal takes to rise from low to high (or fall back), usually measured between 10% and 90% (or 20% and 80%) of the voltage swing. CTS keeps it under a maximum.
Expert
A slow clock edge makes flip-flops respond later and raises their setup and hold requirements, wastes power while a gate’s pull-up and pull-down transistors briefly conduct together, and makes the edge’s timing more sensitive to noise. Clock nets usually get a tighter limit than data nets.
Explained in Clock tree synthesis (Design Flow).