Beginner

A single shared road that all the parts of a chip take turns using.

Novice

A shared set of wires that connects several blocks. Only one transfer can use it at a time, so it is simple and cheap, but all the blocks share its bandwidth.

Expert

Every block sees every transfer, which made the bus the natural base for snooping cache coherence. As more blocks attach, waiting for a turn (arbitration) and the long, heavily loaded wires limit its speed and bandwidth.

Explained in Architecture (Design Flow).

See also: Crossbar, Network-on-chip (NoC).

All 896 terms →