AMAT (average memory access time)
Beginner
On average, how long the processor waits each time it asks memory for something.
Novice
. Example: a 1-cycle cache that misses 10% of the time, with 20 cycles to fetch a missed line, averages cycles. With several cache levels, the miss penalty is itself the average access time of the next level.
Expert
A first-order latency model. Processors that keep working past a miss (out-of-order cores), or that have several misses outstanding at once, hide part of the penalty, so the real slowdown is smaller than AMAT suggests for those cores and close to it for simple in-order ones.
Explained in Architecture (Design Flow).
See also: Cache, 3Cs (compulsory, capacity, conflict misses).