Glossary

Adaptive SoC

Beginner

One chip that holds normal processor cores, a rewirable FPGA part, and often special engines for AI math.

Novice

A system on a chip that combines hard processor cores, FPGA fabric and, increasingly, arrays of small vector or AI engines, joined by an on-chip network. AMD uses the name for its Versal family; Altera and Microchip build similar SoC FPGAs.

Expert

Hard CPUs for control, fabric for bit-level and streaming logic, a vector-engine array for dense MACs, hard memory controllers and a hard NoC. The goal is to move most of the area into hard blocks, where the FPGA–ASIC gap is small, while keeping fabric for what changes.

Explained in Where FPGAs win (Architectures).

See also: SoC, FPGA, Hard IP (FPGA).

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